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ltc4089-3 1 40893f for more information www.linear.com/4089-3 applications hvin boost hvenin sw 4.7f 10f 4.7f 1f timer clprog ltc4089-3 gnd prog hvout hvpr out bat 0.1f 100k 2k 5v (nom) from usb cable v bus high (6v-36v) voltage input li-ion battery + 1k to ldos r egs , etc. 40893 tao1a v out (typ) v bat + 0.3v 5v v bat available input hv input usb only bat only 10h 0.1f usb power manager with high voltage switching charger the lt c ? 4089-3 is a usb power manager plus high voltage li-ion battery charger. this device controls the total cur - rent used by the usb peripheral for operation and battery charging. battery charge current is automatically reduced such that the sum of the load current and the charge cur - rent does not exceed the programmed input current limit. the ltc4089-3 also accommodates high voltage power supplies, such as 12v ac/dc wall adapters, firewire, or automotive power. the ltc4089-3 provides an adaptive output that tracks the battery voltage for high eficiency charging from the high voltage input. this 3.95v version of the the standard ltc4089 is intended for applications which have extended battery lifetime requirements or those that require high temperature (approximately >60c) operation or stor - age. under these conditions, a reduced loat voltage will trade-off initial cell capacity for the beneit of increased capacity retention over the life of the battery. the charge current is programmable and an end-of-charge status output ( chrg ) indicates full charge. also featured are programmable total charge time, an ntc thermistor input used to monitor battery temperature while charging and automatic recharging of the battery. l , lt, ltc and ltm are registered trademarks and bat-track, powerpath and thinsot are trademarks of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents including 6522118, 6700364, 7733061. n portable usb devicesgps receivers, cameras, mp3 players, pdas n seamless transition between power sources: li-ion battery, usb, and 6v to 36v external supply n high ef?ciency 1.2a charger from 6v to 36v input with adaptive output control n 3.95v float voltage improves battery lifespan and high temperature safety margin n load dependent charging from usb input guarantees current compliance n 215m internal ideal diode plus optional external ideal diode controller provides low loss power path when external supply/usb not present n constant-current/constant-voltage operation with thermal feedback to maximize charging rate without risk of overheating n selectable 100% or 20% current limit (e.g., 500ma/ 100ma) from usb input n preset 3.95v charge voltage with 0.8% accuracy n c/10 charge current detection output n ntc thermistor input for temperature qualiied charging n tiny (6mm 3mm 0.75mm) 22-lead dfn package ltc4089 high voltage battery charger ef?ciency battery voltage (v) 2.5 40 efficiency (%) 45 55 60 65 9075 3 3.5 40893 ta01b 50 80 85 70 4 4.5 cc current = 970mano output load figure 10 schematic with r prog = 52k hvin = 8vhvin = 12v hvin = 24v hvin = 36v typical application description features downloaded from: http:///
ltc4089-3 2 40893f for more information www.linear.com/4089-3 terminal voltage boost ...................................................... C0.3v to 50v boost above sw ..................................................... 25v hvin, hven .............................................. C0.3v to 40v in, out, hvout t < 1ms and duty cycle < 1% .................. C0.3v to 7v dc ............................................................ C0.3v to 6v bat .............................................................. C0.3v to 6v ntc, timer, prog, clprog ....... C0.3v to (v cc + 0.3v) chrg , hpwr, susp, hvpr ......................... C0.3v to 6v pin current, dc in, out, bat (note 6) ............................................... 2.5a operating temperature range.................. C40c to 85c maximum operating junction temperature .......... 110c storage temperature range ................... C65c to 150c (notes 1, 2, 3, 4, 5) symbol parameter conditions min typ max units usb input current limitv in usb input supply voltage in l 4.35 5.5 v i in input bias current i bat = 0 (note 7) suspend mode; susp = 5v l l 0.5 50 1 100 ma a pin configuration absolute maximum ratings 2221 20 19 18 17 16 15 14 13 12 12 3 4 5 6 7 8 9 1011 hvenhvin boost sw hvout timer susp hpwr clprog out in top view 23 djc package 22-lead (6mm 3mm) plastic dfn gndgnd hvout v c ntc vntc hvpr chrgprog gate bat t jmax = 110c, ja = 4c/w exposed pad (pin 23) is gnd, must be soldered to pcb order information lead free finish tape and reel part marking package description temperature range ltc4089edjc-3#pbf ltc4089edjc-3#trpbf 40893 22-lead (6mm 3mm) plastic dfn C40c to 85c consult ltc marketing for parts speciied with wider operating temperature ranges. consult ltc marketing for information on non-standard lead based inish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel speciications, go to: http://www.linear.com/tapeandreel/ electrical characteristics the l denotes the speci?cations which apply over the full operating temperature range, otherwise speci?cations are at t a = 25c. hvin = 12v, boost = 17v, v in = 5v, v b at = 3.7v, hven = 12v, hpwr = 5v, r prog = 100k, r clprog = 2k, susp = 0v, unless otherwise noted. ltc4089 options part number float voltage ntc hot threshold bat-track? adaptive hv output ltc4089 4.2v 29% v vntc yes ltc4089-1 4.1v 32.6% v vntc no ltc4089-3 3.95v 32.6% v vntc yes ltc4089-5 4.2v 29% v vntc no downloaded from: http:///
ltc4089-3 3 40893f for more information www.linear.com/4089-3 electrical characteristics the l denotes the speci?cations which apply over the full operating temperature range, otherwise speci?cations are at t a = 25c. hvin = 12v, boost = 17v, v in = 5v, v b at = 3.7v, hven = 12v, hpwr = 5v, r prog = 100k, r clprog = 2k, susp = 0v, unless otherwise noted. symbol parameter conditions min typ max units i lim current limit r clprog = 2k, hpwr = 5v r clprog = 2k, hpwr = 0v l l 475 90 500 100 525 110 ma ma i in(max) maximum input current limit (note 8) 2.4 a r on on resistance v in to v out i out = 80ma load 0.215 v clprog clprog pin voltage r clprog = 2k r clprog = 1k l l 0.98 0.98 1.00 1.00 1.02 1.02 v v i ss soft-start inrush current in 5 ma/s v clen input current limit enable threshold voltage (v in C v out ) (v in C v out ) v in rising (v in C v out ) v in falling 20 C80 50 C50 80 C20 mv mv v uvlo input undervoltage lockout v in powers part, rising threshold l 3.6 3.8 4 v dv uvlo input undervoltage lockout hysteresis v in rising C v in falling 130 mv high voltage regulator v hvin hvin supply voltage 6 36 v i hvin hvin bias current not switching shutdown; hven = 0v 1.9 0.01 2.5 2 ma a v out output voltage with hvin present assumes hvout to out connection 3.45 v bat +0.3 4.6 v v hvuvlo high voltage input undervoltage lockout v hvin rising 4.7 5 v f sw switching frequency v hvout > 3.95v v hvout = 0v 685 750 35 815 khz khz dc max maximum duty cycle l 88 95 % i sw(max) switch current limit (note 9) 1.5 1.95 2.3 a v sat switch v cesat i sw = 1a 330 mv i lk switch leakage current 2 a v swd minimum boost voltage above sw i sw = 1a 1.85 2.2 v i bst boost pin current i sw = 1a 30 50 ma battery management v bat input voltage bat 4.3 v i bat battery drain current v bat = 4.05v, charging stopped suspend mode; susp = 5v v hvin = v in = 0v, bat powers out, no load l l l 15 22 60 27 35 100 a a a v float regulated output voltage i bat = 2ma i bat = 2ma; (0c C 85c) 3.915 3.910 3.95 3.95 3.985 3.990 v v i chg current mode charge current r prog = 100k, no load r prog = 50k, no load; (0c C 85c) l 465 900 500 1000 535 1080 ma ma i chg(max) maximum charge current (note 8) 1.2 a v prog prog pin voltage r prog = 100k r prog = 50k l l 0.98 0.98 1.00 1.00 1.02 1.02 v v k eoc ratio of end-of-charge current to charge current v bat = v float (3.95v) l 0.085 0.1 0.11 ma/ma i trikl trickle charge current v bat = 2v, r prog = 100k 35 50 60 ma v trikl trickle charge threshold voltage l 2.75 2.9 3 v v cen charger enable threshold voltage (v out C v bat ) falling; v bat = 4v (v out C v bat ) rising; v bat = 4v 55 80 mv mv v rechrg recharge battery threshold voltage v float C v rechrg l 60 95 130 mv t timer timer accuracy v bat = 4.05v C10 10 % recharge time percent of total charge time 50 % downloaded from: http:///
ltc4089-3 4 40893f for more information www.linear.com/4089-3 symbol parameter conditions min typ max units low battery trickle charge time percent of total charge time, v bat < 2.8v 25 % t lim junction temperature in constant temperature mode 105 c internal ideal dioder fwd incremental resistance, v on regulation i bat = 100ma 125 m r dio(on) on resistance v bat to v out i bat = 600ma 215 m v fwd voltage forward drop (v bat - v out ) i bat = 5ma i bat = 100ma i bat = 600ma l 10 30 55 160 50 mv mv mv v off diode disable battery voltage 2.8 v i fwd load current limit, for v on regulation 550 ma i d(max) diode current limit 2.2 a external ideal diodev fwd(ext) external diode forward voltage 20 mv logicv ol output low voltage ( chrg , hvpr ) i sink = 5ma l 0.1 0.4 v v ih input high voltage hven, susp, hpwr pin low to high 2.3 v v il input low voltage hven, susp, hpwr pin high to low 0.3 v i pulldn logic input pull down current susp, hpwr 2 a i hven hven pin bias current v hven = 2.3v v hven = 0v 6 0.01 20 0.1 a a v chg(sd) charger shutdown threshold voltage on timer l 0.14 0.4 v i chg(sd) charger shutdown pull-up current on timer v timer = 0v l 5 14 a ntc i vntc vntc pin current v vntc = 2.5v l 1.4 2.5 3.5 ma v vntc vntc bias voltage i vntc = 500a l 4.4 4.85 v i ntc ntc input leakage current v ntc = 1v 0 1 a v cold cold temperature fault threshold voltage rising threshold hysteresis 0.738?v vntc 0.018?v vntc v v v hot hot temperature fault threshold voltage falling threshold hysteresis 0.326?v vntc 0.015?v vntc v v v dis ntc disable voltage ntc input voltage to gnd (falling) hysteresis l 75 100 35 125 mv mv note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: v cc is the greater of v in , v out or v bat note 3: all voltage values are with respect to gnd. note 4: this ic includes overtemperature protection that is intended to protect the device during momentary overload conditions. junction temperatures will exceed 110c when overtemperature protection is active. continuous operation above the speciied maximum operating junction temperature may result in device degradation or failure. note 5: the ltc4089-3 is guaranteed to meet speciied performance from 0c to 85c and are designed, characterized and expected to meet these extended temperature limits, but are not tested at C40c and 85c. note 6: guaranteed by long term current density limitations. note 7: total input current is equal to this speciication plus 1.002 ? i bat where i bat is the charge current. note 8: accuracy of programmed current may degrade for currents greater than 1.5a.note 9: current limit guaranteed by design and/or correlation to static test. slope compensation reduces current limit at high duty cycle. electrical characteristics the l denotes the speci?cations which apply over the full operating temperature range, otherwise speci?cations are at t a = 25c. hvin = 12v, boost = 17v, v in = 5v, v b at = 3.7v, hven = 12v, hpwr = 5v, r prog = 100k, r clprog = 2k, susp = 0v, unless otherwise noted. downloaded from: http:///
ltc4089-3 5 40893f for more information www.linear.com/4089-3 time (min) 0 v bat , v out , v chrg (v) i bat (a) 2 3 200 40893 g03 10 50 100 150 54 0.6 0.90.3 0 1.51.2 v bat v out v chrg i bat termination c/10 1250mahhv in = 12v r prog = 50k typical performance characteristics v float load regulation battery regulation (float) voltage vs temperature battery current and voltage vs time charging from usb, i b at vs v b at charge current vs temperature (thermal regulation) ideal diode current vs forward voltage and temperature (no external device) ideal diode current vs forward voltage and temperature with external device high voltage regulator ef?ciency vs output load t a = 25c, unless otherwise speci?ed. i bat (ma) 0 3.75 v float (v) 3.80 3.85 3.90 3.95 4.00 4.05 200 400 600 800 40893 g01 1000 r prog = 34k temperature (c) C50 v float (v) 3.945 3.950 3.955 25 75 40893 g02 3.940 3.935 3.930 C25 0 50 3.960 3.965 3.970 100 v in = 5v i bat = 2ma v bat (v) 0 0 i bat (ma) 100 300 400 500 1 2 2.5 4.5 40893 g04 200 0.5 1.5 3 3.5 4 600 v in = 5v v out = no load r prog = 100k r clprog = 2k hpwr = 5v temperature (c) C50 i bat (ma) 400 500 600 25 75 40893 g05 300 200 C25 0 50 100 125 100 0 v in = 5v v bat = 3.5v ja = 50c/w v fwd (mv) 0 0 i out (ma) 100 300 400 500 1000 700 50 100 40893 g06 200 800 900 600 150 200 v bat = 3.7v v in = 0v C50c 0c 50c 100c 0 3000 4000 5000 80 40853 g07 20001000 2500 3500 45001500 500 0 20 40 60 100 v fwd (mv) i out (ma) v bat = 3.7v v in = 0v si2333 pfet C50c 0c 50c 100c i out (a) 0 efficiency (%) 80 90 100 0.8 40893 g08 7060 75 85 9565 55 50 0.2 0.4 0.6 1.0 figure 10 schematic v bat = 4.21v (i bat = 0) hvin = 8vhvin = 12v hvin = 24v hvin = 36v downloaded from: http:///
ltc4089-3 6 40893f for more information www.linear.com/4089-3 typical performance characteristics high voltage regulator maximum load current, l = 10h high voltage regulator maximum load current, l = 33h high voltage regulator switch voltage drop high voltage regulator switch frequency high voltage regulator frequency foldback high voltage regulator soft-start high voltage switch current limit high voltage regulator typical minimum input voltage t a = 25c, unless otherwise speci?ed. v in (v) 5 1.61.5 1.4 1.3 1.2 1.1 1.0 0.9 20 30 40893 g10 10 15 25 35 i out (a) minimum typical v in (v) 5 1.81.6 1.5 1.4 1.3 1.2 1.1 1.0 0.9 20 30 40893 g11 10 15 25 35 i out (a) minimum typical switch current (a) 0 v ce(sw) (mv) 150 450 500 550 0.4 0.8 1.0 40893 g12 50 350 250 100 400 0 300 200 0.2 0.6 1.4 1.2 1.6 1.8 t a = 25c t a = 85c t a = C40c temperature (c) frequency (khz) 720 760 800 125 40893 g13 680640 700 740 780660 620 600 C25 C50 25 0 75 100 150 50 hvout (v) 0 switching frequency (khz) 400 600 5 40893 g14 200 0 1 3 2 4 800300 500100 700 shdn pin voltage (v) 0 0 switch current limit (a) 0.2 0.6 0.8 1.0 2.01.4 0.50 1 1.25 40893 g15 0.4 1.6 1.81.2 0.25 0.75 1.50 1.75 2 duty cycle (%) 0 current limit (a) 1.6 1.8 2.0 80 40893 g16 1.41.2 1.5 1.7 1.91.3 1.1 1.0 20 10 40 30 60 70 90 50 100 t a = C40c t a = C5c t a = 25c t a = 90c load current (ma) 1 5.8 input voltage (v) 6.0 6.2 6.4 6.6 10 100 1000 40893 g17 5.6 5.45.2 5.0 6.8 7.0 to start to run downloaded from: http:///
ltc4089-3 7 40893f for more information www.linear.com/4089-3 input connect waveforms typical performance characteristics input disconnect waveforms response to hpwr wall connect waveforms wall disconnect waveforms response to suspend high voltage regulator load transient high voltage regulator load transient t a = 25c, unless otherwise speci?ed. 1ms/div v in 5v/div v out 5v/div i in 0.5a/div i bat 0.5a/div 40893 g18 v bat = 3.85v i out = 100ma 1ms/div v in 5v/div v out 5v/div i in 0.5a/div i bat 0.5a/div 40893 g19 v bat = 3.85v i out = 100ma 100s/div hpwr 5v/div i in 0.5a/div i bat 0.5a/div 40893 g20 v bat = 3.85v i out = 50ma 1ms/div wall 5v/div v out 5v/div i wall 0.5a/div i bat 0.5a/div 40893 g21 v bat = 3.85v i out = 100ma r prog = 100k 1ms/div wall 5v/div v out 5v/div i wall 0.5a/div i bat 0.5a/div 40893 g22 v bat = 3.85v i out = 100ma r prog = 100k 100s/div susp 5v/div v out 5v/div i in 0.5a/div i bat 0.5a/div 40893 g23 v bat = 3.85v i out = 50ma 20s/div h vout 50mv/div i out 0.5a/div 40893 g24 20s/div h vout 50mv/div i l 0.5a/div 40893 g25 downloaded from: http:///
ltc4089-3 8 40893f for more information www.linear.com/4089-3 gnd (pins 1, 2, exposed pad pin 23): ground. tie the gnd pin to a local ground plane below the ltc4089-3 and the circuit components. the exposed package pad is ground and must be soldered to the pc board for proper functionality and for maximum heat transfer (use several vias directly under the ltc4089-3). hvout (pins 3, 18) : voltage output of the high voltage regulator. when suficient voltage is present at hvout, the low voltage power path from in to out will be discon - nected and the hvpr pin will be pulled low to indicate that a high voltage wall adapter has been detected. the ltc4089-3 high voltage regulator will maintain just enough differential voltage between hvout and bat to keep the battery charger mosfet out of dropout (typically 300mv from out to bat). hvout should be bypassed with at least 10f to gnd. connect pins 3 and 18 with a resistance no greater than 1 . v c (pin 4): leave the v c pin loating or bypass to ground with a 10pf capacitor. this optional 10pf capacitor reduces hvout ripple in discontinuous mode. ntc (pin 5): input to the ntc thermistor monitoring circuit. the ntc pin connects to a negative temperature coeficient thermistor which is typically co-packaged with the battery pack to determine if the battery is too hot or too cold to charge. if the battery temperature is out of range, charging is paused until the battery temperature re-enters the valid range. a low drift bias resistor is re - quired from in to ntc and a thermistor is required from ntc to ground. to disable the ntc function, the ntc pin should be grounded. connect the ntc pin to ground to disable this feature. this will disable all of the ltc4089-3 ntc functions. vntc (pin 6): output bias voltage for ntc. a resistor from this pin to the ntc pin will bias the ntc thermistor. hvpr (pin 7): high voltage present output. active low open-drain output pin. a low on this pin indicates that the high voltage regulator has suficient voltage to charge the battery. this feature is disabled if no power is present on hvin, in or bat (i.e., below uvlo thresholds). chrg (pin 8): open-drain charge status output. when the battery is being charged, the chrg pin is pulled low by an internal n-channel mosfet. when the timer runs out or the charge current drops below 10% of the programmed charge current or the input supply is removed, the chrg pin is forced to a high impedance state. prog (pin 9): charge current program. connecting a resistor, r prog , to ground programs the battery charge current. the battery charge current is programmed as follows: i chg (a) = 50,000v r prog gate (pin 10): external ideal diode gate pin. this pin can be used to drive the gate of an optional external pfet con - nected between bat (drain) and out (source). by doing so, the impedance of the ideal diode between bat and out can be reduced. when not in use, this pin should be left loating. it is important to maintain a high impedance on this pin and minimize all leakage paths. bat (pin 11): connect to a single cell li-ion battery. this pin is used as an output when charging the battery and as an input when supplying power to out. when the out pin potential drops below the bat pin potential, an ideal diode function connects bat to out and prevents v out from dropping more than 100mv below v bat . a precision internal resistor divider sets the inal loat (charging) potential on this pin. the internal resistor divider is disconnected when in and hvin are in undervoltage lockout. in (pin 12): input supply. connect to usb supply, v bus . input current to this pin is limited to either 20% or 100% of the current programmed by the clprog pin as de - termined by the state of the hpwr pin. charge current (to the bat pin) supplied through the input is set to the current programmed by the prog pin but will be limited by the input current limit if charge current is set greater than the input current limit. pin functions downloaded from: http:///
ltc4089-3 9 40893f for more information www.linear.com/4089-3 out (pin 13): voltage output. this pin is used to provide controlled power to a usb device from either usb v bus (in), an external high voltage supply (hvin), or the battery (bat) when no other supply is present. the high voltage supply is prioritized over the usb v bus input. out should be bypassed with at least 4.7f to gnd.clprog (pin 14): current limit program and input cur - rent monitor. connecting a resistor, r clprog , to ground programs the input to output current limit. the current limit is programmed as follows: i cl (a) = 1000v r clprog in usb applications, the resistor r clprog should be set to no less than 2.1k. the voltage on the clprog pin is always proportional to the current lowing through the in to out power path. this current can be calculated as follows: i in (a) = v clprog r clprog ? 1000 hpwr (pin 15): high power select. this logic input is used to control the input current limit. a voltage greater than 2.3v on the pin will set the input current limit to 100% of the current programmed by the clprog pin. a voltage less than 0.3v on the pin will set the input current limit to 20% of the current programmed by the clprog pin. a 2a pull-down current is internally connected to this pin to ensure it is low at power up when the pin is not being driven externally. susp (pin 16): suspend mode input. pulling this pin above 2.3v will disable the power path from in to out. the supply current from in will be reduced to comply with the usb speciication for suspend mode. both the ability to charge the battery from hvin and the ideal diode function (from bat to out) will remain active. suspend mode will reset the charge timer if v out is less than v bat while in suspend mode. if v out is kept greater than v bat , such as when the high voltage input is present, the charge timer will not be reset when the part is put in suspend. a 2a pull-down current is internally applied to this pin to ensure it is low at power-up when the pin is not being driven externally. timer (pin 17): timer capacitor. placing a capacitor, c timer , to gnd sets the timer period. the timer period is: t timer (hours) = c timer ? r prog ? 3hours 0.1f ? 100k charge time is increased if charge current is reduced due to undervoltage current limit, load current, thermal regulation and current limit selection (hpwr). shorting the timer pin to gnd disables the battery charging functions. sw (pin 19): the sw pin is the output of the internal high voltage power switch. connect this pin to the inductor, catch diode and boost capacitor. boost (pin 20): the boost pin is used to provide a drive voltage, higher than the input voltage, to the internal bipolar npn power switch. hvin (pin 21): the hvin pin supplies current to the inter - nal high voltage regulator and to the internal high voltage power switch. the presence of a high voltage input takes priority over the usb v bus input (i.e., when a high volt - age input supply is detected, the usb in to out path is disconnected). this pin must be locally bypassed. hven (pin 22): the hven pin is used to disable the high voltage input path. tie to ground to disable the high voltage input or tie to at least 2.3v to enable the high voltage path. if this feature is not used, tie to the hvin pin. this pin can also be used to soft-start the high voltage regulator; see the applications information section. pin functions downloaded from: http:///
ltc4089-3 10 40893f for more information www.linear.com/4089-3 C + soft-start 0.25v soft-start2 C + C + C + C + too cold ntc current limit too hot 0.1v ntc enable v ntc ntc 10k 100k 100k C + hpwr clprog inprog chg 1v 500ma/100ma 2a C + C + current control oscillator charge control control logic voltage detect counter oscillator ta die temp 105c i lim 2.8v battery uvlo 3.85vrecharge uvlo in out bat i chg bat uv rechrg hold reset ntcerr clk eoc c/10 C + C + 2a gnd1, 2 susp 2k 3.6v in driver hvout out gate bat bat hvpr timer chrg stop 40893 bd 1v cl i lim cntl enable C + eda d1 c3 l1 i in 1000 c4 r3 10pf hven hvinv c cc/cv regulator charger enable C + C + 4.25v (rising) 3.15v (falling) C + 1.8v rs q c1 enable C ++ 350mv 75mv (rising) 25mv (falling) gm boost q1 d2 sw 25mv 25mvideal diode q driver + C + C + C + C 21 4 22 12 14 15 9 6 5 16 8 17 11 10 13 7 3 19 20 block diagram downloaded from: http:///
ltc4089-3 11 40893f for more information www.linear.com/4089-3 operation the ltc4089-3 is a complete powerpath? controller for battery-powered usb applications. the ltc4089-3 is designed to receive power from a low voltage source (e.g., usb or 5v wall adapter), a high voltage source (e.g., firewire/ieee1394, automotive battery, 12v wall adapter, etc.), and a single-cell li-ion battery. it can then deliver power to an application connected to the out pin and a battery connected to the bat pin (assuming that an external supply other than the battery is present). power supplies that have limited current resources (such as usb v bus supplies) should be connected to the in pin which has a programmable current limit. battery charge current will be adjusted to ensure that the sum of the charge current and load current does not exceed the programmed input current limit (see figure 1). an ideal diode function provides power from the battery when output / load current exceeds the input current limit or when input power is removed. powering the load through the ideal diode instead of connecting the load directly to the battery allows a fully charged battery to remain fully charged until external power is removed. once external power is removed the output drops until the ideal diode is forward biased. the forward biased ideal diode will then provide the output power to the load from the battery. the ltc4089-3 also includes a high voltage switching regulator which has the ability to receive power from a high voltage input. this input takes priority over the usb v bus input (i.e., if both hvin and in are present, load current and charge current will be delivered via the high voltage path). when enabled, the high voltage regulator regulates the hvout voltage using a 750khz constant frequency, current mode regulator. an external pfet between hvout (drain) and out (source) is turned on via the hvpr pin allowing out to charge the battery and/or supply power to the application. the ltc4089-3 maintains approximately 300mv between the out pin and the bat pin. (refer to block diagram) hvout out gate bat bat out hvpr 40893 f01 C + eda d1 l1 cc/cv regulator charger high voltage buck regulator usb current limit enable C + C + c1 hvin in q1 sw 25mv 25mvideal diode 4.25v (rising) 3.15v (falling) 75mv (rising) 25mv (falling) + load li-ion + C + C + C 21 12 11 10 13 7 18 19 figure 1. simpli?ed powerpath block diagram downloaded from: http:///
ltc4089-3 12 40893f for more information www.linear.com/4089-3 i in i load(ma) 0 300 400 500 400 500 300 40893 f02a 200100 100 200 0 current (ma) i load i bat (charging) i bat (ideal diode) i in i load(ma) 0 60 80 100 80 100 60 40893 f02b 4020 20 40 0 current (ma) i load i bat (charging) i bat (ideal diode) i load (ma) 0 300 400 500 400 500 300 40893 f02c 200100 100 200 0 current (ma) i in i load i bat = i chg i bat = i cl = i out i bat (charging) i bat (ideal diode) input current limitwhenever the input power path is enabled (i.e., susp = 0v and hvin = 0v) and power is available at in, power is delivered to out. the current limit and charger control circuits of the ltc4089-3 are designed to limit input cur - rent as well as control battery charge current as a function of i out . the input current limit, i cl , can be programmed using the following formula: i cl = 1000 r clprog ? v clprog ?? ? ?? ? = 1000v r clprog where v clprog is the clprog pin voltage (typically 1v) and r clprog is the total resistance from the clprog pin to ground. for best stability over temperature and time, 1% metal ilm resistors are recommended. the programmed battery charge current, i chg , is deined as: i chg = 50,000 r prog ? v prog ?? ? ?? ? = 50,000v r prog figure 2. input and battery currents as a function of load current input current, i in , is equal to the sum of the bat pin output current and the out pin output current. v clprog will typically servo to 1v, however, if i out + i bat < i cl then v clprog will track the input current according to the following equation: i in = i out + i bat = v clprog r clprog ? 1000 the current limiting circuitry in the ltc4089-3 can and should be conigured to limit current to 500ma for usb applications (selectable using the hpwr pin and pro - grammed using the clprog pin). the ltc4089-3 reduces battery charge current such that the sum of the battery charge current and the load current does not exceed the programmed input current limit (one- ifth of the programmed input current limit when hpwr is low, see figure 2). the battery charge current goes to zero when load current exceeds the programmed input current limit (one-ifth of the limit when hpwr is low). even if the battery charge current is set to exceed the allowable usb current, the usb speciication will not be violated. (a) high power mode/full charge r prog = 100k and r clprog = 2k (b) low power mode/full charge r prog = 100k and r clprog = 2k (c) high power mode with i cl = 500ma and i chg = 250ma r prog = 200k and r clprog = 2k operation downloaded from: http:///
ltc4089-3 13 40893f for more information www.linear.com/4089-3 the battery charger will reduce its current as needed to ensure that the usb speciication is not exceeded. if the load current is greater than the current limit, the output voltage will drop to just under the battery voltage where the ideal diode circuit will take over and the excess load current will be drawn from the battery. in usb applications, the minimum value for r clprog should be 2.1k. this will prevent the input current from exceeding 500ma due to ltc4089-3 tolerances and quiescent cur - rents. a 2.1k clprog resistor will give a typical current limit of 476ma in high power mode (hpwr = 1) or 95ma in low power mode (hpwr = 0). when susp is driven to a logic high, the input power path is disabled and the ideal diode from bat to out will supply power to the application. high voltage step down regulator the power delivered from hvin to hvout is controlled by a 750khz constant frequency, current mode step down regulator. an external p-channel mosfet directs this power to out and prevents reverse conduction from out to hvout (and ultimately hvin). a 750khz oscillator enables an rs lip-lop, turning on the internal 1.95a power switch q1. an ampliier and comparator monitor the current lowing between the hvin and sw pins, turning the switch off when this current reaches a level determined by the voltage at v c . an error ampliier servos the v c node to maintain approximately 300mv between out and bat. by keeping the voltage across the battery charger low, eficiency is optimized because power lost to the battery charger is minimized and power available to the external load is maximized. if the bat pin voltage is less than approximately 3.3v, then the error ampliier will servo the v c node to provide a constant hvout output voltage of about 3.6v. an active clamp on the v c node provides current limit. the v c node is also clamped to the voltage on the hven pin; soft-start is implemented by a voltage ramp at the hven pin using an external resistor and capacitor. an internal regulator provides power to the control circuitry. this regulator includes an undervoltage lockout to prevent switching when hvin is less than about 4.7v. the hven pin is used to disable the high voltage regulator. hvin input current is reduced to less than 2a and the external p-channel mosfet disconnects hvout from out when the high voltage regulator is disabled. the switch driver operates from either the high voltage input or from the boost pin. an external capacitor and diode are used to generate a voltage at the boost pin that is higher than the input supply. this allows the driver to fully saturate the internal bipolar npn power switch for eficient operation. when hvout is below 3.95v the operating frequency is reduced. this frequency foldback helps to control the regulator output current during start-up and overload. ideal diode from bat to out the ltc4089-3 has an internal ideal diode as well as a controller for an optional external ideal diode. if a battery is the only power supply available, or if the load current exceeds the programmed input current limit, then the battery will automatically deliver power to the load via an ideal diode circuit between the bat and out pins. the ideal diode circuit (along with the recommended 4.7f capacitor on the out pin) allows the ltc4089-3 to handle large transient loads and wall adapter or usb v bus con - nect/disconnect scenarios without the need for large bulk capacitors. the ideal diode responds within a few micro - seconds and prevents the out pin voltage from dropping signiicantly below the bat pin voltage. a comparison of the i-v curve of the ideal diode and a schottky diode can be seen in figure 3. if the input current increases beyond the programmed input current limit additional current will be drawn from the battery via the internal ideal diode. furthermore, if power to in (usb v bus ) or hvin (high voltage input) is removed, then all of the application power will be provided by the battery via the ideal diode. a 4.7f capacitor at operation downloaded from: http:///
ltc4089-3 14 40893f for more information www.linear.com/4089-3 out is suficient to keep a transition from input power to battery power from causing signiicant output voltage droop. the ideal diode consists of a precision ampliier that enables a large p-channel mosfet transistor whenever the voltage at out is approximately 20mv (v fwd ) below the voltage at bat. the resistance of the internal ideal diode is approximately 200m . if this is suficient for the application then no external components are necessary. however, if more conductance is needed, an external p-channel mosfet can be added from bat to out. the gate pin of the ltc4089-3 drives the gate of the pfet for automatic ideal diode control. the source of the external mosfet should be connected to out and the drain should be connected to bat. in order to help protect the external mosfet in over-current situations, it should be placed in close thermal contact to the ltc4089-3. battery charger the battery charger circuits of the ltc4089-3 are designed for charging single-cell lithium-ion batteries. featuring an internal p-channel power mosfet, the charger uses a constant-current/constant-voltage charge algorithm with programmable current and a programmable timer for charge termination. charge current can be programmed up to 1.2a. the inal loat voltage accuracy is 0.8% typical. no blocking diode or sense resistor is required when powering either the in or the hvin pins. the chrg open-drain status output provides information regarding the charging status of the ltc4089-3 at all times. an ntc input provides the option of charge qualiication using battery temperature. an internal thermal limit reduces the programmed charge current if the die temperature attempts to rise above a preset value of approximately 105c. this feature protects the ltc4089-3 from excessive temperature, and allows the user to push the limits of the power handling capabil - ity of a given circuit board without risk of damaging the ltc4089-3. another beneit of the ltc4089-3 thermal limit is that charge current can be set according to typical, not worst-case, ambient temperatures for a given application with the assurance that the charger will automatically reduce the current in worst-case conditions. the charge cycle begins when the voltage at the out pin rises above the battery voltage and the battery volt - age is below the recharge threshold. no charge current actually lows until the out voltage is 100mv above the bat voltage. at the beginning of the charge cycle, if the battery voltage is below 2.8v, the charger goes into trickle charge mode to bring the cell voltage up to a safe level for charging. the charger goes into the fast charge constant-current mode once the voltage on the bat pin rises above 2.8v. in constant-current mode, the charge current is set by r prog . when the battery approaches the inal loat voltage, the charge current begins to decrease as the ltc4089-3 switches to constant-voltage mode. when the charge current drops below 10% of the programmed charge current while in constant-voltage mode the chrg pin assumes a high impedance state. operation figure 3. ltc4089-3 versus schottky diode forward voltage drop constant i 0n constant r 0n constant v 0n v fwd i max forward voltage (v) 40893 f03 i fwd 0 current (a) slope: 1/r dio(on) slope: 1/r fwd schottky diode ltc4089 downloaded from: http:///
ltc4089-3 15 40893f for more information www.linear.com/4089-3 an external capacitor on the timer pin sets the total minimum charge time. when this time elapses the charge cycle terminates and the chrg pin assumes a high impedance state, if it has not already done so. while charging in constant-current mode, if the charge current is decreased by thermal regulation or in order to maintain the programmed input current limit the charge time is automatically increased. in other words, the charge time is extended inversely proportional to the actual charge current delivered to the battery. for li-ion and similar batteries that require accurate inal loat potential, the internal bandgap reference, voltage ampliier and the resistor divider provide regulation with 0.8% accuracy. trickle charge and defective battery detection at the beginning of a charge cycle, if the battery volt - age is low (below 2.8v) the charger goes into trickle charge reducing the charge current to 10% of the full- scale current. if the low battery voltage persists for one quarter of the total charge time, the battery is assumed to be defective, the charge cycle is terminated and the chrg pin output assumes a high impedance state. if for any reason the battery voltage rises above ~2.8v the charge cycle will be restarted. to restart the charge cycle (i.e., when the dead battery is replaced with a discharged battery), simply remove the input voltage and reapply it or cycle the timer pin to 0v. programming charge current the formula for the battery charge current is: i chg = i prog ? 50,000 = v prog r prog ? 50,000 where v prog is the prog pin voltage and r prog is the total resistance from the prog pin to ground. keep in mind that when the ltc4089-3 is powered from the in pin, the programmed input current limit takes precedent over the charge current. in such a scenario, the charge current cannot exceed the programmed input current limit. for example, if typical 500ma charge current is required, calculate: r prog = 1v 500ma ? 50,000 = 100k for best stability over temperature and time, 1% metal ilm resistors are recommended. under trickle charge condi - tions, this current is reduced to 10% of the full-scale value. the charge timer the programmable charge timer is used to terminate the charge cycle. the timer duration is programmed by an external capacitor at the timer pin. the charge time is typically: t timer (hours) = c timer ? r prog ? 3hours 0.1f ? 100k the timer starts when an input voltage greater than the undervoltage lockout threshold level is applied or when leaving shutdown and the voltage on the battery is less than the recharge threshold. at power-up or exiting shutdown with the battery voltage less than the recharge threshold the charge time is a full cycle. if the battery is greater than the recharge threshold the timer will not start and charging is prevented. if after power-up the battery voltage drops below the recharge threshold, or if after a charge cycle the battery voltage is still below the recharge threshold, the charge time is set to one-half of a full cycle. the ltc4089-3 has a feature that extends charge time automatically. charge time is extended if the charge current in constant-current mode is reduced due to load current or thermal regulation. this change in charge time is inversely proportional to the change in charge current. as the ltc4089-3 approaches constant-voltage mode the charge current begins to drop. this change in charge current is due to normal charging operation and does not affect the timer duration. operation downloaded from: http:///
ltc4089-3 16 40893f for more information www.linear.com/4089-3 consider, for example, a usb charge condition where r clprog = 2k, r prog = 100k and c timer = 0.1f. this corresponds to a three hour charge cycle. however, if the hpwr input is set to a logic low, then the input current limit will be reduced from 500ma to 100ma. with no ad - ditional system load, this means the charge current will be reduced to 100ma. therefore, the termination timer will automatically slow down by a factor of ive until the charger reaches constant-voltage mode (i.e., v bat = 4.2v) or hpwr is returned to a logic high. the charge cycle is automatically lengthened to account for the reduced charge current. the exact time of the charge cycle will depend on how long the charger remains in constant-current mode and/or how long the hpwr pin remains a logic low. once a timeout occurs and the voltage on the battery is greater than the recharge threshold, the charge current stops, and the chrg output assumes a high impedance state if it has not already done so. connecting the timer pin to ground disables the battery charger. chrg status output pin when the charge cycle starts, the chrg pin is pulled to ground by an internal n-channel mosfet capable of driving an led. when the charge current drops below 10% of the programmed full charge current while in constant-voltage mode, the pin assumes a high impedance state, but charge current continues to low until the charge time elapses. if this state is not reached before the end of the program - mable charge time, the pin will assume a high impedance state when a timeout occurs. the chrg current detection threshold can be calculated by the following equation: i detect = 0.1v r prog ? 50,000 = 5000v r prog for example, if the full charge current is programmed to 500ma with a 100k prog resistor the chrg pin will change state at a battery charge current of 50ma. note: the end-of-charge (eoc) comparator that moni - tors the charge current latches its decision. therefore, the irst time the charge current drops below 10% of the programmed full charge current while in constant-voltage mode, it will toggle chrg to a high impedance state. if, for some reason the charge current rises back above the threshold, the chrg pin will not resume the strong pull- down state. the eoc latch can be reset by a recharge cycle (i.e., v bat drops below the recharge threshold) or toggling the input power to the part. ntc thermistor?battery temperature charge quali?cation the battery temperature is measured by placing a nega - tive temperature coeficient (ntc) thermistor close to the battery pack. the ntc circuitry is shown in figure 4. to use this feature, connect the ntc thermistor (r ntc ) between the ntc pin and ground and a resistor (r nom ) from the ntc pin to vntc. r nom should be a 1% resistor with a value equal to the value of the chosen ntc thermistor at 25c (this value is 10k for a vishay nths0603n02n1002j thermistor). the ltc4089-3 goes into hold mode when the resistance (r hot ) of the ntc thermistor drops to 0.48 times the value of r nom , or approximately 4.8k, which should be at 45c. the hold mode freezes the timer and stops the charge cycle until the thermistor indicates a re - turn to a valid temperature. as the temperature drops, the figure 4. ntc circuit C + C + r nom 10k r ntc 10k ntc vntc 6 0.1v ntc_enable 40893 f04 ltc4089-3 too_coldtoo_hot 0.74 ? vntc 0.326 ? vntc C + 5 operation downloaded from: http:///
ltc4089-3 17 40893f for more information www.linear.com/4089-3 operation resistance of the ntc thermistor rises. the ltc4089-3 is designed to go into hold mode when the value of the ntc thermistor increases to 2.82 times the value of r nom . this resistance is r cold . for a vishay nths0603n02n1002j thermistor, this value is 28.2k which corresponds to ap - proximately 0c. the hot and cold comparators each have approximately 2c of hysteresis to prevent oscillation about the trip point. grounding the ntc pin will disable the ntc function. current limit undervoltage lockout an internal undervoltage lockout circuit monitors the input voltage and disables the input current limit circuits until v in rises above the undervoltage lockout threshold. the current limit uvlo circuit has a built-in hysteresis of 125mv. furthermore, to protect against reverse current in the power mosfet, the current limit uvlo circuit disables the current limit (i.e., forces the input power path to a high impedance state) if v out exceeds v in . if the current limit uvlo comparator is tripped, the current limit circuits will not come out of shutdown until v out falls 50mv below the v in voltage. charger undervoltage lockout an internal undervoltage lockout circuit monitors the v out voltage and disables the battery charger circuits until v out rises above the undervoltage lockout threshold. the battery charger uvlo circuit has a built-in hysteresis of 125mv. furthermore, to protect against reverse current in the power mosfet, the charger uvlo circuit keeps the charger shut down if v bat exceeds v out . if the charger uvlo comparator is tripped, the charger circuits will not come out of shutdown until v out exceeds v bat by 50mv. suspend the ltc4089-3 can be put in suspend mode by forcing the susp pin greater than 2.3v. in suspend mode, the ideal diode function from bat to out is kept alive. if power is applied to the hvin pin, then charging will be unaffected. current drawn from the in pin is reduced to 50a. suspend mode is intended to comply with the usb power speciication mode of the same name. downloaded from: http:///
ltc4089-3 18 40893f for more information www.linear.com/4089-3 usb and 5v wall adapter power although the ltc4089-3 is designed to draw power from a usb port, a higher power 5v wall adapter can also be used to power the application and charge the battery (higher voltage wall adapters can be connected directly to hvin). figure 5 shows an example of combining a 5v wall adapter and a usb power input. with its gate grounded by 1k, p-channel mosfet mp1 provides usb power to the ltc4089-3 when 5v wall power is not available. when 5v wall power is available, d1 both supplies power to the ltc4089-3, pulls the gate of mn1 high to increase the charge current (by increasing the input current limit), and pulls the gate of mp1 high to disable it and prevent conduction back to the usb port. expected application load current. for robust operation in fault conditions, the saturation current should be ~2.3a. to keep eficiency high, the series resistance (dcr) should be less than 0.1 . table 1 lists several vendors and types that are suitable. table 1: inductor vendors vendor url part series inductance (h) size (mm) sumida www.sumida.com cdrh5d28 8.2, 10 6 6 3 cdrh6d38 10 7 7 4 tdk www.tdk.com slf6028t 10 6 6 2.8 toko www.toko.com d63lcb 10 6.3 6.3 3 catch diodedepending on load current, a 1a to 2a schottky diode is recommended for the d1 catch diode. the diode must have a reverse voltage rating equal to, or greater than, the maximum input voltage. the on semiconductor mbrm140 and the diodes inc. dfls140/160/240 are good choices. high voltage regulator capacitor selection bypass the hvin pin of the ltc4089-3 circuit with a 1f, or higher value ceramic capacitor of x7r or x5r type. y5v types have poor performance over temperature and applied voltage and should not be used. a 1f ceramic is adequate to bypass the high voltage input and will easily handle the ripple current. however, if the input power source has high impedance, or there is signiicant inductance due to long wires or cables, additional bulk capacitance may be necessary. this can be provided with a low performance electrolytic capacitor. figure 5. usb or 5v wall adapter power applications information 2k 1k mn1 2.87k 59k in prog clprog ltc4089-3 bat + mp1 d1 i chg li-ion battery 5v wall adapter 850ma i chg usb power 500ma i chg 40893 f05 inductor selection and maximum output currenta good choice for the inductor value is l = 10h. with this value the maximum load current will be 1a. the rms current rating of the inductor must be greater than the maximum load current and its saturation current should be about 30% higher. note that the maximum load current will be the programmed charge current plus the largest downloaded from: http:///
ltc4089-3 19 40893f for more information www.linear.com/4089-3 the high voltage regulator output capacitor control s output ripple, supplies transient load currents, and stabilizes the regulator control loop. ceramic capacitors have very low equivalent series resistance (esr) and provide the best ripple performance. a good value is 10f. use x5r or x7r types, and note that a ceramic capacitor biased with v hvout will have less than its nominal capacitance. table?2 lists several capacitor vendors. table 2: capacitor vendors vendor phone url part series comments panasonic (714) 373-7366 www.panasonic.com ceramic, polymer, tantalum eef series kemet (864) 963-6300 www.kemet.com ceramic, tantalum t494, t495 sanyo (408) 749-9714 www.sanyovideo.com ceramic, polymer, tantalum poscap murata (404) 436-1300 www.murata.com ceramic avx www.avxcorp.com ceramic, tantalum tps series taiyo yuden (864) 963-6300 www.taiyo-yuden.com ceramic boost pin considerations capacitor c3 and diode d2 (see block diagram) are used to generate a boost voltage that is higher than the input voltage. in most cases, a 0.1f capacitor and fast-switch - ing diode (such as the 1n4148 or 1n914) will work well. the boost pin must be at least 2.2v above the sw pin for proper operation. high voltage regulator soft-start the hven pin can be used to soft-start the high voltage regulator and reduce the maximum input current during start-up. a voltage ramp at the hven pin can be created by driving the pin through an external rc ilter (see figure 6). by choosing a large rc time constant, the peak start-up current will not overshoot the current that is required to regulate the output. choose the value of the resistor so that it can supply 20a when the hven pin reaches 2.3v. figure 6. using the hven pin to soft-start the high voltage regulator. applications information run 15k 0.1f hven gnd 40893 f06 ltc4089-3 alternate ntc thermistors the ltc4089-3 ntc trip points were designed to work with thermistors whose resistance-temperature charac - teristics follow vishay dales r-t curve 2. the vishay nths0603n02n1002j is an example of such a thermis - tor. however, vishay dale has many thermistor products that follow the r-t curve 2 characteristic in a variety of sizes. furthermore, any thermistor whose ratio of r cold to r hot is about 6.0 will also work (vishay dale r-t curve?2 shows a ratio of 2.815/0.4839 = 5.82). power conscious designs may want to use thermistors whose room temperature value is greater than 10k. vishay dale has a number of values of thermistor from 10k to 100k that follow the r-t curve 2. using these as indicated in the ntc thermistor section will give temperature trip points of approximately 3c and 42c, a delta of 39c. this delta in temperature can be moved in either direc - tion by changing the value of r nom with respect to r ntc . increasing r nom will move both trip points to lower temperatures. likewise, a decrease in r nom with respect to r ntc will move the trip points to higher temperatures. to calculate r nom for a shift to lower temperature, for example, use the following equation: r nom = r cold 2.816 ? r ntc at 25 c downloaded from: http:///
ltc4089-3 20 40893f for more information www.linear.com/4089-3 where r cold is the resistance ratio of r ntc at the desired cold temperature trip point. to shift the trip points to higher temperatures use the following equation: r nom = r hot 0.484 ? r ntc at 25 c where r hot is the resistance ratio of r ntc at the desired hot temperature trip point. the following example uses a 100k r-t curve 1 thermistor from vishay dale. the difference between the trip points is 39c, from beforeand the desired cold trip point of 0c, would put the hot trip point at 39c. the r nom needed is calculated as follows: r nom = r cold 2.816 ? r ntc at 25 c = 3.2662.816 ? 100k ? = 116k ? the nearest 1% value for r nom is 115k. this is the value used to bias the ntc thermistor to get cold and hot trip points of approximately 0c and 44c, respectively. to extend the delta between the cold and hot trip points, a resistor (r1) can be added in series with r ntc (see figure 7). the values of the resistors are calculated as follows: r nom = r cold ? r hot 2.816 ? 0.484 r1 = 0.484 2.816 ? 0.484 ?? ? ?? ? ? r cold ? r hot [ ] ? r hot where r nom is the value of the bias resistor, r hot and r cold are the values of r ntc at the desired temperature trip points. continuing the forementioned example with a desired hot trip point of 50c: r nom = r cold ? r hot 2.816 ? 0.484 = 100k ? (3.266 ? 0.3602) 2.816 ? 0.484 = 124.6k,124k nearest 1% r1 = 100k ? 0.484 2.816 ? 0.484 ?? ? ?? ? ? 3.266 ? 0.3602 ( ) ? 0.3602 ?? ?? ? ?? ?? ? = 24.3k the inal solution is shown in figure 7, where r nom = 124k, r1 = 24.3k and r ntc = 100k at 25c figure 7. modi?ed ntc circuit applications information C + C + r nom 124k r ntc 100k r124.3k ntc vntc 15 0.1v ntc_enable 4089 f07 too_coldtoo_hot 0.738 ? vntc 0.326 ? vntc C + 14 ltc4089-3 downloaded from: http:///
ltc4089-3 21 40893f for more information www.linear.com/4089-3 power dissipation and high temperature considerations the die temperature of the ltc4089-3 must be lower than the maximum rating of 110c. this is generally not a con - cern unless the ambient temperature is above 85c. the total power dissipated inside the ltc4089-3 depends on many factors, including input voltage (in or hvin), battery voltage, programmed charge current, programmed input current limit, and load current. in general, if the ltc4089-3 is being powered from in the power dissipation can be calculated as follows: p d = (v in C v bat ) ? i bat + (v in Cv out ) ? i out where p d is the power dissipated, i bat is the battery charge current, and i out is the application load current. for a typical application, an example of this calculation would be: p d = (5v C 3.7v) ? 0.4a + (5v C 4.75v) ? 0.1a = 545mw this example assumes v in = 5v, v out = 4.75v, v bat = 3.7v, i bat = 400ma, and i out = 100ma resulting in slightly more than 0.5w total dissipation. if the ltc4089-3 is being powered from hvin, the power dissipation can be estimated by calculating the regulator power loss from an eficiency measurement, and subtract - ing the catch diode loss. p d = (1 ? ) ? (v hvout ? (i bat + i out )) ? v d ? 1 ? v hvout v hvin ?? ? ?? ? ? (i bat + i out ) + 0.3v ? i bat where is the eficiency of the high voltage regulator and v d is the forward voltage of the catch diode at i = i bat + i out . the irst term corresponds to the power lost in converting v hvin to v hvout , the second term subtracts the catch diode loss, and the third term is the power dissipated in the battery charger. for a typical application, an example of this calculation would be: p d = (1 ? 0.87) ? 4v ? (0.7a + 0.3a) [ ] ? 0.4v ? 1 ? 4v 12v ?? ? ?? ? ? (0.7a + 0.3a) + 0.3v ? 0.7a = 463mw this example assumes 87% eficiency, v hvin = 12v, v bat = 3.7v (v hvout is about 4v), i bat = 700ma, i out = 300ma resulting in less than 0.5w total dissipation. to prevent power dissipation of this magnitude from causing high die temperature, it is important to solder the exposed backside of the package to a ground plane. this ground should be tied to other copper layers below with thermal vias; these layers will spread the heat dis sipated by the ltc4089-3v. additional vias should be placed near the catch diodes. adding more copper to the top and bottom layers, and tying this copper to the internal planes with vias, can reduce thermal resistance further. with these steps, the thermal resistance from die (i.e., junction) to ambient can be reduced to ja = 40c/w. the power dissipation in the other power compo - nentscatch diodes, mosfets, boost diodes and induc - torscauses additional copper heating and can further increase the ambient temperature of the ic. board layout considerations as discussed in the previous section, it is critical that the exposed metal pad on the backside of the ltc4089-3 package be soldered to the pc board ground. further - more, proper operation and minimum emi requires a careful printed circuit board (pcb) layout. note that large, switched currents low in the power switch (between the hvin and sw pins), the catch diode and the hvin input capacitor. these components, along with the inductor and output capacitor, should be placed on the same side of the circuit board, and their connections should be made on that layer. place a local, unbroken ground plane below these components. the loop formed by these components should be as small as possible. additionally, the sw and boost nodes should be kept as small as possible. figure 8 shows the recommended component placement with trace and via locations. applications information downloaded from: http:///
ltc4089-3 22 40893f for more information www.linear.com/4089-3 high frequency currents, such as the high voltage input current of the ltc4089, tend to ind their way along the ground plane on a mirror path directly beneath the incident path on the top of the board. if there are slits or cuts in the ground plane due to other traces on that layer, the current will be forced to go around the slits. if high frequency currents are not allowed to low back through their natural least-area path, excessive voltage will build up and radiated emissions will occur. see figure 9. figure 8. suggested board layout figure 9. ground currents follow their incident path at high speed. slices in the ground plane cause high voltage and increased emissions. minimize d1, l1,c3, u1, sw pin loop minimize trace length u1 thermal pad soldered to pcb. vias connected to all gnd planes without thermal relief. c1 and d1 gnd pads side-by-side and seperated with c3 gnd pad applications information 40893 f09 v in and v hvin bypass capacitor many types of capacitors can be used for input bypassing, however, caution must be exercised when using multilayer ceramic capacitors. because of the self-resonant and high q characteristics of some types of ceramic capacitors, high voltage transients can be generated under some start-up conditions, such as from connecting the charger input to a hot power source. for more information, refer to application note 88. battery charger stability considerations the constant-voltage mode feedback loop is stable without any compensation when a battery is connected with low impedance leads. excessive lead length, however, ma y add enough series inductance to require a bypass capacitor of at least 1f from bat to gnd. furthermore, a 4.7f capacitor with a 0.2 to 1 series resistor to gnd is recommended at the bat pin to keep ripple voltage low when the battery is disconnected. downloaded from: http:///
ltc4089-3 23 40893f for more information www.linear.com/4089-3 please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. information furnished by linear technology corporation is believed to be accurate and reliable. how- ever, no responsibility is assumed for its use. linear technology corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. package description 3.00 0.10 (2 sides) note:1. drawing proposed to be made variation of version (wxxx) in jedec package outline m0-229 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on top and bottom of package note: 1. dimensions are in millimeters 2. apply solder mask to areas that are not soldered 3. drawing is not to scale 0.40 0.05 pin #1 notchr0.30 typ or 0.25mm 45 chamfer bottom viewexposed pad 1.65 0.10 (2 sides) 0.75 0.05 r = 0.115 typ r = 0.10 typ 1 22 1211 pin 1 top mark (note 6) 0.200 ref 0.00 C 0.05 (djc) dfn 0605 6.00 0.10 (2 sides) 0.25 0.05 0.889 0.889 0.50 bsc 5.35 0.10 (2 sides) r = 0.10 recommended solder pad pitch and dimensions 1.65 0.05 (2 sides) 2.20 0.05 0.70 0.05 3.60 0.05 packageoutline 0.25 0.05 0.50 bsc 5.35 0.05 (2 sides) 0.889 0.889 djc package 22-lead plastic dfn (6mm 3mm) (reference ltc dwg # 05-08-1714 rev ?) downloaded from: http:///
ltc4089-3 24 40893f for more information www.linear.com/4089-3 ? linear technology corporation 2013 lt 0313 ? printed in usa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com/4089-3 part number description comments power management ltc3455 dual dc/dc converter with usb power manager and li-ion battery charger seamless transition between power sources: usb, wall adapter and battery; 95% eficient dc/dc conversion ltc4055 usb power controller and battery charger charges single cell li-ion batteries directly from a usb port, thermal regulation, 200m ideal diode, 4mm 4mm qfn16 package ltc4066 usb power controller and li-ion battery charger with low-loss ideal diode charges single cell li-ion batteries directly from a usb port, thermal regulation, 50m ideal diode, 4mm 4mm qfn24 package ltc4085 usb power manager with ideal diode controller and li-ion charger charges single cell li-ion batteries directly from a usb port, thermal regulation, 200m ideal diode with <50m option, 4mm 3mm dfn14 package related parts hvin sw v in 6v to 36v gnd usb 4.35v to 5.5v l1 10h slf6028t-100m1r3 40893 f10 v c gnd ltc4089-3 gnd boost susp + hvouthvout hvpr out gate bat chrg vntc ntc hven c1 1f 50v c54.7f 6.3v c4 0.1f 10% r3 2.1k 1% r4 71.5k 1% c922f 50v r11m 1% c71000pf 50v v in e1e2 e3 r21 prog timerclprog d2 sd101aws c2 0.1f 6.3v d1dlfs160 c322f 6.3v c6 4.7f 6.3v r7 680 d3 hvpr red r61k 1% r5 10k 1% r1010k 1% q1si2333ds q2si2333ds r8 680 d4 chgr grn c84.7f 6.3v r91 e16h vout e4out gnd e6 li-ion+ e7 gnd e9 chgr 19 2122 12 15 16 17 14 9 20 318 7 13 10 11 8 6 5 on off 12 3 jp1 vin off on 12 3 jp3 usb on/off usb 500ma100ma 12 3 jp2 current in hpwr 4 2 1 10pf figure 10. typical application diagram applications information downloaded from: http:///

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